Flash memory semiconductor devices are used in wide array of electronic apparati, such as computers, digital cameras, and personal digital assistants. In all of such applications, increasing memory capacity and reducing electrical consumption are desirable. The primary approach to increasing capacity and decreasing power requirements has been making smaller each succeeding generation of devices. The current technology is less than 0.25-μm in geometry. As the circuit elements become smaller, problems have arisen relating to the interference between different circuit elements.
The former generation of flash memory semiconductor devices used local oxidation of silicon (LOCOS) technology to isolate circuit elements. LOCOS has been replaced in the current generation by shallow trench isolation (STI) technology to isolate circuit elements. In STI technology, shallow trenches are formed between circuit elements, such as metal oxide semiconductor field effect transistors (MOSFETs). MOSFETs include a source and a drain region of doped semiconductor material between which current traverses. This current is controlled by a gate which is insulated from the source and drain regions by a thin layer of insulating material. If, as is conventional, multiple gate layers insulated from each other by insulating layers exist, a “floating” gate is produced which gains its signal through the principle of quantum tunneling. In STI technology, the source, drain, and floating gate are formed between the shallow trenches etched into the substrate of semiconductor materials, such as silicon, germanium, or gallium arsenide. A thin layer of an insulating material such as silicon oxide (SiO) is formed over the area between the trenches to insulate the active region. The gate, often a layer of polycrystalline silicon, is formed over this insulating layer. In operation a small charge on this gate can control a larger flow between the source and the drain. The active region width is approximately the distance between the source and drain areas that is under the gate area.
A problem has arisen in STI technology where thinning portions of an insulating layer or tunnel oxide layer adjacent relatively thinning corners of the STI structures has developed. These thinning portions are difficult to measure and quantify. The presence of thinning portions may be made by monitoring the Fowler-Nordheim (F-N) tunneling current. However, such a measurement gives no measure of nor provides any information about the total physical overlap area between the floating gate and the active region.
This overlap has a large impact on the programming current distribution and core gain. As a result, an outstanding need is seen to exist for a method of fabricating a flash memory semiconductor device by determining the active region width accurately and a STI flash memory semiconductor device thereby fabricated.